Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Electronic technologies such as digital computers, calculators, audio devices, video equipment and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, these systems comprise a solid state integrated microelectronic circuit. A solid state integrated microelectronic circuit is a collection of interconnected circuit elements (e.g., resistors, diodes, transistors, etc.) fabricated on or within a single continuous substrate referred to as a chip.
Very large scale integration (VLSI) is utilized to achieve significant levels of functionality in a single application specific integrated circuit (ASIC). ASICs are often comprised of components organized in numerous blocks that perform specified functions directed to the overall operability of the ASIC. Many of the numerous blocks that perform specified functions directed to the overall operability of the ASIC are not directly accessible from the external pins during normal operations and are considered hidden or buried within the chip. The importance of ASICs in numerous applications and the significant complexities involved in the design and manufacturing of ASICs make it imperative that significant and reliable testing procedures be implemented to ensure an ASIC is functioning correctly. However, as a practical matter most test vectors are introduced to a chip at external pins and since internal devices and internal buses are buried within a chip, they are not accessible during normal operations from external pins, and thus limited in their ability to be reliably tested.
FIG. 1 is a block diagram of prior art ASIC 100, a powerful multifunctional device in which an internal PCI bus is always visible at external pins. ASIC 100 comprises external PCI bus interface 101 and combined multifunction device 102. Combined multifunction device 102 comprises PCI-to-PCI bridge 120, internal PCI bus 130, PCI agent block 140, PCI agent block 150 and PCI agent block 160. Each PCI block includes a bus I/F unit and a device functional block. Internal PCI bus 130, is coupled to PCI agent block 140, PCI agent block 150, PCI agent block 160 and PCI-to-PCI bridge 120 which is coupled to external PCI bus interface 101. In prior art embodiments such as ASIC 100 in which an internal PCI bus is connected to external components such as an external PCI bus, applying test vectors to internal PCI agent blocks is relatively easy but extremely inefficient. For example in ASIC 100 test vectors can be applied to the external PCI bus interface and they are transmitted through PCI-to-PCI bridge 120 and internal PCI bus 130 to PCI agent block 140, PCI agent block 150 or PCI agent block 160. Test vectors are packets of bits that act like stimuli to activate chip functions and causing the components of the chip to perform certain operations and the re interrogate the results.
While this approach in which an internal PCI bus and PCI agent blocks coupled to the PCI internal bus are permanently and completely visible does permit testing of the internal bus and PCI agent blocks coupled to the internal PCI bus, a large number of valuable external interface resources (e.g., usually between 45 and 52 pins) are expended to provide this permanent visibility. Such a large expenditure of valuable chip resources for testing that may well only be performed infrequently during the life of a chip is an expenditure of resources that is usually not outweighed by the benefits and is inefficient. Therefore design constraints often limit the ability to include an external bus interface coupled to a PCI to PCI bridge that provides permanent and complete visibility to the operations of internal agent blocks. Thus most designs include internal device that can not communicate with external devices in a normal operation mode.
FIG. 2 is a block diagram of prior art ASIC 200, another powerful multifunctional device. ASIC 200 comprises an external PCI bus interface (not shown) and combined multifunction device 202. Combined multifunction device 202 comprises internal PCI bus 230, PCI agent block 240, PCI agent block 250 and PCI agent block 260. Each PCI block includes a bus I/F unit and a device functional block. Internal PCI bus 230, is coupled to PCI agent block 240, PCI agent block 250, and PCI agent block 260. In prior art embodiments such as ASIC 200, in which an internal PCI bus is not connected to external components such as an external PCI bus, applying test vectors to internal PCI agent blocks is relatively difficult. For example, test multiplexes and boundary scan are two traditional prior art testing approaches utilized to test internal agent blocks of a system such as ASIC 200.
Test multiplexer techniques typically involve taking all the, connections on each agent block out to the chip's periphery or external pins via multiplexers. The multiplexers are inserted in the communication paths between internal agent blocks. The multiplexers are devices that are utilized to select between one signal such as normal operations and another signal such as test vectors. In normal operations the multiplexers are configured so the chip proceeds with its normal functionality and "normal" signals appear at the chip's periphery or external pins. However, by putting the chip into a special test mode, the multiplexers are manipulated to make signals at connections to certain internal hidden agent blocks appear at the periphery external pins of the chip. Thus, the buried agent blocks can be accessed and tested by applying test vectors to the appropriate external pins.
This test multiplexer approach causes problems in systems comprising PCI devices that have very high timing constraints, especially in faster ASICs that are running at 66 megahertz and higher. Inserting test multiplexers right in the path of such timing critical signals is often unacceptable for performance reasons and typically leads to a reduction in the operating frequency of the path simply to accommodate the extra delay introduced by the multiplexers. In addition, each set of devices or PCI agent blocks within a chip require its own set of multiplexers effectively using up valuable chip resources just inserting the test multiplexers.
Full scan or boundary scan testing involves inserting special scan flip flops around the periphery of a chip. The special scan flip flops are coupled to internal buses and serially linked to each other in a path around the chip. Bit patterns to and from external devices are serially shifted into and out of the special scan flip flops. Data in the special shift registers is loaded onto and retrieved from internal buses and internal agent blocks, effectively permitting the internal agent blocks to be interrogated through this serial scan flip flop interface. Although this approach does provide a level of internal agent block testing it has numerous disadvantages.
Usually, the scan flip flops impose themselves right on the critical path of the design and often interfere with the operations of a chip to such extent that using them is impractical. Typically, scan flip flops are very slow and similar to test multiplexers introduce delays that impact performance of critical timing sequences. Scan flip flops also often introduce a delay because they are a clocked part and they require that a clocked element be placed at each signal to be interrogated. If a chip has asynchronous signals in out of a block, for example a serial port, and serial elements are driven in the asynchronous interfaces they may simply cease to function, making a scan flip flop an unviable solution in some instances.
In addition to introducing delays, scan flip flop testing technique have other disadvantages. For example, scan flip flops are typically very special scan flip flops and are not supported by all chip path technologies. In other situations a design may require very specific types of interfaces that preclude scan based register elements because access to the PCI signals for the application of preset factor tests may be difficult or impossible. In particular, PCI test vectors are usually PCI cycles such as reads and writes and utilizing boundary scan flip flops typically requires a special mechanism right on the PCI bus which in some instances may simply not work functionally. Sometimes buried agent blocks do not exist in very convenient forms and a design may be in gates without boundary scan support. A vendor may provide a design in a net list form that does not provide an understanding of the internal operation of a device and it is impractical to intelligently replace register elements within this block with scan registers without adequate knowledge.
What is required is a system and method to effectively and efficiently access internal agent blocks for testing. The system and method should permit standard test vectors to be used during manufacturing, validation and debugging procedures to exercise the functionality of chip's internal components and test its operations. The system and method should not be dependent on JTAG, boundary scan, full scan or test multiplexers.